Diamond Level Area Reduction: ICs with fewer than 100,000,000 Transistors*

Diamond Level Area Reduction: ICs with fewer than 100,000,000 Transistors*

Is the parametric yield of your IC already 100% ? And does your IC contain fewer than 100,000,000 transistors?*

If so, I will come to your work site and, for only $85,000, will cut the transistor area of the IC by 10% or more in less than a month, without adversely affecting its parametric yield. 

What if I don't achieve the above target in less than a month ? In that case, you pay nothing.

 

Terms and Conditions: 

The work month has to be a calendar month, starting the first, second or third day of the month, and ending the last day of the month.

On the first day of work, you have to provide me with all of the following:

1. An HSpice, Spectre or Eldo (SCAM** Simulator) netlist that you used to run Monte Carlo simulations.

2. Whatever statistical analysis you have performed with SCAM** Statistical Vaporware***, including mismatch analysis if any.

3. An office environment (cubicle or office), with a computer and access at least one license to all of the tools mentioned above.

4. The ability for me to install NGSpice and whatever other software I need.

 

Note: this solution won't be available until March 1, 2036.

 

To get started, email achab@abdenourachab.com with the following subject line: Diamond Level Solution: Area Reduction of IC with fewer than 100,000,000 Transistors*

 

* Transistor Accounting: the number of transistors is the number of transistors that will ultimately be in the manufactured circuit. So, if you have a netlist with 90,000 transistors and a behavioral model that will ultimately be implemented in manufacturing with billions of transistors, that's a billions transistors circuit, NOT an IC with few than 100,000 transistors.

** SCAM: Defined in the glossary

*** Statistical Vaporware: Defined in the glossary


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