Emerald Summer Internship: Robust Design of an IC with fewer than 10,000,000 Transistors*

Emerald Summer Internship: Robust Design of an IC with fewer than 10,000,000 Transistors*

Could you use some help with your Statistical Circuit Design issues for ICs with transistor counts of between one billion and ten billion transistors?

And are you in a position to hire a PhD Student in Electrical Engineering as a Full Time Summer Intern?

If so, then our Emerald Summer Internship is what you have been looking for.

 

Terms and Conditions: 

1) The internship will start mid May and end mid August.

2) I will work full time at your company site, from 9 PM to 6 PM every week day except national and company holidays.

3) During those three months, I will provide one of our Emerald Level Robust IC Design Solutions (Emerald Level Parametric Yield OptimizationEmerald Level Chip Area Reduction or Emerald Level Performance Variability Reduction) and our Emerald Level Corporate Training.

4) The pay needs to be at least $64,021 a month.

5) Your standard Assignment of Intellectual Property agreement needs to be customized as follows:

    5.a) Whatever EDA software I develop during the summer, outside of your company site and without using your company resources, will belong to me.

    5.b) The sanitized version of whatever training material I develop during the summer, whether or not I do it on your company site and/or using your company resources, will belong to me, and a perpetual non transferable license for use will be granted to your company at no cost. "Sanitized version" means removing all proprietary information from the training that belongs to your company.

6) Meet the terms of our Emerald level solution.

This Emerald Level Internship will be available the following ten summers: from Summer 2031 through Summer 2040, inclusive.

 

To get started, select one of our Emerald Level Internship, email achab@abdenourachab.com using the following subject line: Emerald Level Internship.

 

* Transistor Accounting: the number of transistors is the number of transistors that will ultimately be in the manufactured circuit. So, if you have a netlist with 9,000,000 transistors and a behavioral model that will ultimately be implemented in manufacturing with billions of transistors, that's a billions transistors circuit, NOT an analog cell with few than 10,000,000 transistors.


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