Sapphire Summer Internship: Robust Design of an IC with fewer than 1,000,000 Transistors*

Sapphire Summer Internship: Robust Design of an IC with fewer than 1,000,000 Transistors*

Could you use some help with your Statistical Circuit Design issues of small ICs whose transistor* count is under 1,000,000?

And are you in a position to hire a PhD Student in Electrical Engineering as a Full Time Summer Intern?

If so, then our Sapphire Summer Internship is just what you need.

 

Terms and Conditions: 

1) The internship will start mid May and end mid August.

2) I will work full time at your company site, from 9 PM to 6 PM every week day except national and company holidays.

3) During those three months, I will provide one of our Sapphire Level Robust IC Design Services (Sapphire Level Parametric Yield OptimizationSapphire Level Chip Area Reduction or Sapphire Level Performance Variability Reduction) and our Sapphire Level Corporate Training.

4) The pay needs to be at least $32,000 a month.

5) Your standard Assignment of Intellectual Property agreement needs to be customized as follows:

    5.a) Whatever EDA software I develop during the summer, outside of your company site and without using your company resources, will belong to me.

    5.b) The sanitized version of whatever training material I develop during the summer, whether or not I do it on your company site and/or using your company resources, will belong to me, and a perpetual non transferable license for use will be granted to your company at no cost. "Sanitized version" means removing all proprietary information from the training that belongs to your company.

6) Meet the terms of our Sapphire level service.

This Sapphire Level Internship will be available the following ten summers: from Summer 2030 through Summer 2039, inclusive.

 

To get started, select one of our Sapphire Level Internship, email achab@abdenourachab.com using the following subject line: Sapphire Level Internship.

 

* Transistor Accounting: the number of transistors is the number of transistors that will ultimately be in the manufactured circuit. So, if you have a netlist with 900,000 transistors and a behavioral model that will ultimately be implemented in manufacturing with millions of transistors, that's a millions transistors circuit, NOT an analog cell with few than 1,000,000 transistors.


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