Unobtanium Level Solution: Whole Chip Parametric Yield Optimization

Unobtanium Level Solution: Whole Chip Parametric Yield Optimization

Do you have an IC chip for which you are struggling to bring the parametric yield to 100% without significantly increasing design time and/or transistor area ?

If so, I will come to your company site and, for only $100,000, cut the difference between 100% and the parametric yield by two or more in less than a month, without increasing transistor area by more than 10%. So, if, for example, the parametric yield of your chip is currently 50%, I will bring its parametric yield 75% or more. If the parametric yield of your chip is 90%, I will bring it to 95% or more. If you hand me a chip with 98% yield, I will raise the yield to 99% ore more.

What if I don't achieve the above target in less than a month ? In that case, you pay nothing.

 

Terms and Conditions: 

The work month has to be a calendar month, starting the first, second or third day of the month, and ending the last day of the month.

On the first day of work, you have to provide me with all of the following:

1. An HSpice, Spectre or Eldo (SCAM** Simulator) netlist that you used to run Monte Carlo simulations.

2. Whatever statistical analysis you have performed with SCAM** Statistical Vaporware***, including mismatch analysis if any.

3. An office environment (cubicle or office), with a computer and access at least one license to all of the tools mentioned above.

4. The ability for me to install NGSpice and whatever other software I need.

 

Note: this service won't be available until March 1, 2037.

 

To get started, email This email address is being protected from spambots. You need JavaScript enabled to view it. with the following subject line: Bronze Level Service: Parametric Yield Optimization of Analog chips with fewer than 10 Transistors*

 

* SCAM: Defined in the  the glossary

** Statistical Vaporware: Defined in the  the glossary


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