Is the parametric yield of your small IC already 100% ? And does your IC contain fewer than 1,000 transistors?*
If so, I will come to your company site and, for only $8,132 (less than what you would pay an average design engineer for a month), cut the transistor area of the cell by 10% or more in less than a month, without adversely affecting its parametric yield.
What if I don't achieve the above target in less than a month ? In that case, you pay nothing.
Terms and Conditions:
The work month has to be a calendar month, starting the first, second or third day of the month, and ending the last day of the month.
On the first day of work, you have to provide me with all of the following:
1. An HSpice, Spectre or Eldo (SCAM** Simulator) netlist that you used to run Monte Carlo simulations.
2. Whatever statistical analysis you have performed with SCAM** Statistical Vaporware***, including mismatch analysis if any.
3. An office environment (cubicle or office), with a computer and access at least one license to all of the tools mentioned above.
4. The ability for me to install NGSpice and whatever other software I need.
Note: except as part of our Summer Internship programs, the above service won't be available March 1, 2033.
To get started, email achab@abdenourachab.
* Transistor Accounting: the number of transistors is the number of transistors that will ultimately be in the manufactured circuit. So, if you have a netlist with 900 transistors and a behavioral model that will ultimately be implemented in manufacturing with thousands of transistors, that's a thousands transistors circuit, NOT an analog cell with few than 1,000 transistors.
** SCAM: Defined in the the glossary
*** Statistical Vaporware: Defined in the the glossary