Could you use some help with your Statistical Circuit Design issues of small ICs whose transistor* count is under 100?
And are you in a position to hire a PhD Student in Electrical Engineering as a Full Time Summer Intern?
If so, then our Bronze Silver Summer Internship is just what you need.
Terms and Conditions:
1) The internship will start mid May and end mid August.
2) I will work full time at your company site, from 9 PM to 6 PM every week day except national and company holidays.
3) In June, I will provide one of our Bronze Level Robust IC Design Services (Bronze Level Parametric Yield Optimization, Bronze Level Chip Area Reduction or Bronze Level Performance Variability Reduction) and our Bronze Level Corporate Training.
4) In July, I will provide one of our Silver Level Robust IC Design Services (Silver Level Parametric Yield, Silver Level Chip Area Reduction or Silver Level Performance Variability Reduction) and our Silver Level Corporate Training.
5) The pay needs to be at least $2,996 a month.
6) Your standard Assignment of Intellectual Property agreement needs to be customized as follows:
6.a) Whatever EDA software I develop during the summer, outside of your company site and without using your company resources, will belong to me.
6.b) The sanitized version of whatever training material I develop during the summer, whether or not I do it on your company site and/or using your company resources, will belong to me, and a perpetual non transferable license for use will be granted to your company at no cost. "Sanitized version" means removing all proprietary information from the training that belongs to your company.
This Bronze Silver Level Internship will be available the following ten summers: from Summer 2026 through Summer 2035, inclusive.
To get started, select one of our Double Bronze Level Internship, email achab@abdenourachab.
* Transistor Accounting: the number of transistors is the number of transistors that will ultimately be in the manufactured circuit. So, if you have a netlist with 9 transistors and a behavioral model that will ultimately be implemented in manufacturing with thousands of transistors, that's a thousands transistors circuit, NOT an analog cell with few than 10 transistors.