Do you want to never have to hire me again as a Robust IC Design Consultant ?
The first step towards that goal is for your company to purchase our Teaser Level Corporate Training: Robust Design of Analog Cells with fewer than 10 Transistors*.
This training can only be purchased as an add on service to one of our Teaser Level Robust IC Design Services (Teaser Level Parametric Yield Optimization, Teaser Level Chip Area Reduction or Teaser Level Performance Variability Reduction). It CANNOT be purchased separately.
For an additional $970 (due only if the Teaser Level Service is successful), your design and CAD engineers will get 16 hours of on site instruction, as follows:
1) First Friday of the month, 3 PM to 5 PM: Problem Formulation.
Introduce the students (your design and CAD engineers) to the Robust IC Design problem (parametric yield optimization or transistor area reduction) that I will be working on that month as the Teaser Level Service. Explain to the students the importance of studying all the course material at https://RobustICDesignUniversity.com
2) Second Friday of the month, 3 PM to 5 PM: Q&A regarding Robust IC Design 101 from https://RobustICDesignUniversity.com
3) Third Friday of the month, 3 PM to 5 PM: Q&A regarding Robust IC Design 201 from https://RobustICDesignUniversity.com
4) Week after the Third Friday of the month:
4.a) Monday, 3 PM to 5 PM: Hands of resolution of the problem formulated the first Friday of the month.
4.b) Tuesday, 3 PM to 5 PM: Critic and Q&A regarding the resolution of the problem formulated the first Friday of the month.
4.c) Wednesday and Thursday, 3 PM to 5 PM: Bring Your Own Small Analog Cell (< 10 transistors*) to class:
One or two small analog cells will be selected among the ones brought to class by the students, and we will all try to optimize its yield and/or reduce its transistor area.
4.d) General Q&A about Robust IC Design:
Preference will be given to the Robust Design of Small Analog Cells.
But, time permitting, questions about Robust Design of small circuits (<100 transistors*) will be answered too.
To get started, select one of our Teaser Level Robust IC Design Solutions (Teaser Level Parametric Yield Optimization, Teaser Level Chip Area Reduction or Teaser Level Performance Variability Reduction) and, in your email to achab@abdenourachab.
* Transistor Accounting: the number of transistors is the number of transistors that will ultimately be in the manufactured circuit. So, if you have a netlist with 9 transistors and a behavioral model that will ultimately be implemented in manufacturing with thousands of transistors, that's a thousands transistors circuit, NOT an analog cell with few than 10 transistors.